1. Technical Field
This disclosure relates to electronic devices for generating differential oscillating voltages and more particularly to a frequency doubler that doubles the frequency of an input differential oscillating voltage and a related method of generating an output differential oscillating voltage with a frequency double the frequency of an input differential oscillating voltage.
2. Description of the Related Art
A serial communication system includes a receiver (FIG. 1b) and a transmitter (FIG. 1a) in which data are sampled with a clock whose phase is properly determined.
In the transmitter (FIG. 1a), an input stream of data PARALLEL DATA, which may include multiple low-frequency streams, is serialized with a serializer SERIALIZER and transmitted by a driver DRIVER as a stream of serial data OUTPUT DATA into a communication channel. The phase of the serialization clock SER CLK or of any of its submultiples SUB CLK is aligned to that of the incoming data streams PARALLEL DATA and to their associated clock DATA CLK by a phase aligner PHASE ALIGNER that generates a control signal CTRL. A phase interpolator PHASE INTERPOLATOR generates, according to the control signal CTRL, the serialization clock SER CLK with appropriate frequency and phase by combining two clocks in quadrature I and Q.
In the receiver (FIG. 1b), a serial incoming data stream INPUT DATA is typically amplified by a variable gain amplifier VGA and equalized by an analog circuit EQUALIZER. A circuit DFE&SAMPLER performs a decision feedback equalization and samples the equalized data using a sampling clock CLKS provided by a phase interpolator PHASE INTERPOLATOR. The sampled data are transformed into a parallel stream of data PARALLEL DATA by a deserializer DESERIALIZER.
A clock signal DES CLK, extracted from the incoming data stream by the deserializer, is provided together with the parallel stream of data to a clock and data recovery circuit CDR that generates a control signal CTRL. As in the transmitter, the phase interpolator generates, according to the control signal CTRL, the sampling clock CLKS with the correct frequency and phase using the two clocks in quadrature I and Q.
There are various techniques for generating two clocks in quadrature, such as for example the so-called “frequency division” technique [1]. According to this technique, in-phase I and quadrature Q differential voltages are generated from an input differential oscillating voltage V+, V− at a frequency f0 with the circuit of FIG. 2. This circuit uses a frequency doubler ×2, that generates a differential oscillating voltage OUT+, OUT− at a frequency 2f0 double than the input frequency f0, and a frequency divider ÷2 that provides in output two differential oscillating voltages I and Q in quadrature between them.
The frequency divider ÷2 may be a double sampler of the type shown in FIG. 3a, which is substantially a loop composed of two D-latches connected in cascade, that generate the differential oscillating voltage in quadrature Q by sampling twice the differential oscillating voltage I using a clock CK and an inverted replica thereof CK at a frequency 2f0 double than the frequency f0 of the oscillating signal I. The clock CK and the inverted replica thereof CK may be obtained with well-known circuits (not shown in the figure) from the differential oscillating voltage OUT+, OUT−.
The frequency divider ÷2 may be also a ring frequency divider of the type disclosed in [1] and depicted in FIG. 3b together with the transistor-level scheme of one stage. The shown frequency divider is a loop composed of two stages in series, each controlled in phase opposition in respect to the other using the differential outputs of a voltage controlled oscillator that functions at a frequency 2f0 double than the frequency f0 of the oscillating signals I and Q.
The double sampler as well as the ring frequency divider employ a signal oscillating at twice the desired frequency f0. This is inconvenient because the higher the frequency of the oscillating voltage to be generated in a stable and accurate manner, the more complicated the design of the voltage controlled oscillator. Moreover, phase noise of a voltage controlled oscillator may be limited, when the oscillation frequency varies over a broad range, only by increasing power consumption.